Sympariyac (SYMP) delivers compliance-ready DTMF decoding for ADSP-BF5xx. Object code module with a C source wrapper and no framework dependencies.
Power level, frequency deviation, signal duration, pause duration, and input buffer samples per block are user-configurable.
16-bit PCM input format with 8 kHz sampling rate.
Fully re-entrant and multi-instancing capable for multi-threaded systems.
Designed for compliance testing, configurable signal parameters, and a small footprint on ADI Blackfin processors.


Engineered for telecom specs with reliable digit detection and clear diagnostics across tests.


Power level, frequency deviation, signal duration, pause duration, and input block size are user-configurable.


Optimized for low footprint on Blackfin while keeping predictable performance.


Code compatible across ADSP-BF5xx including BF533, BF527, BF518, and BF561.

Power level, frequency deviation, signal duration, pause duration, and input buffer samples per block are user-configurable.

16-bit PCM input with 8 kHz sampling rate.

Object code module with a C source wrapper; no framework dependencies.

Code compatible across the Blackfin processor family ADSP-BF5xx.
Compliant with Bellcore GR-506-CORE, Bellcore TR-TSY-000181, ETSI 300-001, ETSI 201-235, ITU Q.24, Table A-1, AT&T, and NTT specifications.

Coverage aligned to Bellcore, ETSI, ITU Q.24, Table A-1, AT&T, and NTT specifications.
Reports up to 22 unique high level error codes with deterministic diagnostics for DTMF detection.
Actionable diagnostics for detection failures
Clear status for tone, duration, and pause validation
Fully re-entrant and multi-instancing capable
Each module supports the Analog Devices, Inc. (ADI) Blackfin or SHARC Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.
MIPS measured for a DTMF tone of 50ms of digit duration and 50ms of pause duration, Fs=8KHz. On ADSP-BF518, ADSP BF527, ADSP-BF533, ADSP-BF561.
For the optimal memory layout, all code except, adi_slow_noprio_code section is placed in L1. Code in adi_slow_noprio_code section is placed in L3. Data and stack were placed in L1 memory.
Single product evaluation
Compliance-focused teams
Multi-team deployment
Get licensing, compliance details, and delivery options for ADI Blackfin and SHARC processor families.